Spring 2004 CS 352, Professor Mark

Lecture 20 -- Example of out-of-order execution and register renaming
==========

This lecture was given on the chalkboard, so you had to "be there"
to get the full benefit.

First, I described the difference between a superscalar processor
(multiple execution units) and an out-of-order processor.  Out of
order execution is particularly important to allow the processor
to do useful work during a cache miss by a load instruction.

Then, we found RAW, WAW, and WAR dependencies in the following code:

L.D    F6, 34(R2)
L.D    F2, 45(R3)
MULT.D F0, F2, F4
SUB.D  F8, F6, F2
DIV.D  F10, F0, F6
ADD.D  F6, F8, F2

Next, we renamed all of the architectural registers (Fn, Rn) in this
code to physical registers (Pn).  We did this by moving forward through
the code and updating the table that maps architectural registers to
physical registers.

I also explained the general organization of an out-of-order processor,
with a better version of the following figure:


  IN ORDER              Instruction Fetch
  PROCESSING                  |
  (architectural
   registers)                 |
  ...........................\|/...................
                         . Reservation Stations
  OUT-OF-ORDER           . Execution units (ALU's)
  PROCESSING             . Reorder Buffer
  (physical registers)
  .................................................
                           Commit
  IN ORDER                   |
  PROCESSING                \ /
  (architectural
   registers)

Finally, I noted that I was glossing over some details of real out-of-order
processors, but that I primarily wanted to make sure you understood the
following concepts:
   . how dependencies between instructions restrict which instructions
     can be executed out-of-order
   . how register renaming is used to eliminate false (WAW/WAR) dependencies
   . the high-level organization of an out-of-order processor