CS352 Spring 2004 (Professor Mark) -- Schedule, Readings, Handouts

Tentative schedule; subject to revision as the course progresses.
Week
Date
Lec #
Topic 
Reading BEFORE
this date 
Out
In
(Due)
1
1/20
L1
 Introduction; What is Computer Architecture?
 
    
 
1/22
L2
Computer Elements
P&H Chapter 1
 HW #1  
2
1/27
L3
Basic performance concepts
P&H Chapter 2
    
 
1/29
L4
ISA I - Introduction to Instruction Sets
P&H 3.1 - 3.5
    
3
2/3
L5
ISA II - Memory/Control instructions, MIPS/other ISAs

P&H
Appendix A.1-A.6
HW #2
HW #1
 
2/5
L6
ISA III - Different register architectures, ISA principles
P&H 3.6 - 3.15
    
4
2/10
L7
CISC vs. RISC, Microarchitecture elements
P&H B.1 - B.3
    
 
2/12
L8
Computer arithmetic, memory
P&H 4.1 - 4.7
 
 
5
2/17
L9
Datapath and pipelining
P&H 4.8 - 4.12 (skim), Chapter 5 (skim)
HW #3
HW #2
 
2/19
L10
Implementing pipelining
P&H 6.1 - 6.2
    
6
2/24
L11
Data and control hazards, bypassing
 P&H 6.3 - 6.6    
 
2/26
L12
Caches I - Introduction to caching and memory hierarchies
P&H 7.1 - 7.3
HW #4
HW #3
7
3/2
L13
Caches II - Improving cache performance
none
    
 
3/4
L14
Cache wrap-up; Memory system introduction
P&H 7.4 - 7.9
  
HW #4
8
3/9
EX1
Midterm Exam (covers through P&H 7.2)
 
    
 
3/11
L15
Virtual Memory I - Main memory, virtual mem.
 
    
-
-
SPRING BREAK
9
3/23
D1
Discuss midterm exam
 
    
 
3/25
L16
Virtual Memory II -- Page tables, TLBs
 
 HW #5  
10
3/30
L17
Review of virtual memory and caching
 
    
 
4/1
L18
DRAM Organization
 
    
11
4/6
L19
ILP I -- Introduction to Instruction Level Parallelism
 P&H 6.7 - 6.12 HW #6 HW #5
 
4/8
L20
ILP II - OOO execution examples
 
    
12
4/13
L21
ILP III - Speculation and Branch prediction
 
    
 
4/15
L22
Summary of modern processor design
 
 Project (by email 4/18/04) HW #6
13
4/20
L23
Input/Output - Basics, busses, and interconnection
P&H 8.5 - 8.7
    
 
4/22
L24
Multiprocessors I - Granularity, sychronization, and communication models
P&H 9.1 - 9.3
    
14
4/27
L25
Multiprocessors II - Memory coherence.
Also: Fill out course/instructor evaluations.
 P&H 9.4 - 9.7    
 
4/29
L26
Security at the architecture level
 
    
15
5/4
L27
The future: Frontiers in computer architecture
 
    
 
5/6
L28
In Class Review Session
 
   Project
Final
5/17
EX2
Final Exam: 2-5pm, location: UTC 4.122